This application is based on and incorporates herein by reference Japanese Patent Application No. 2001-29979 filed on Feb. 6, 2001.
The present invention relates to a method for manufacturing a semiconductor device in which a gate electrode or an epitaxial layer is formed in a trench formed in a semiconductor layer. The present invention is preferably applicable to a trench-gate type MOSFET (Metal-Oxide-Silicon Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor), in which a gate electrode is formed in a trench.
A trench-gate type MOSFET or an IGBT, in which a gate electrode is formed in a trench, are fabricated with steps of making the trench with RIE (Reactive Ion Etching), forming a gate oxide layer in the trench, and forming a gate electrode by filling the trench coated by the gate oxide layer with a polycrystalline silicon layer. When the trench is made, crystal defects are generated in a crystal adjacent to the trench. The crystal defects cause leak current if the defects exist at a PN junction, or poor breakdown voltage if the defects exist in the vicinity of the gate oxide. Therefore, it is proposed to reduce the crystal defects using sacrificial oxide, CDE (Chemical Dry Etching), isotropic etching with an etchant containing hydrofluoric acid and nitric acid, or the like. However, the above proposed arts are insufficient to remove the defects. In addition, in the proposed arts, the trench is etched horizontally as well, so that the trench horizontal width is increased. Thereby, the aspect ratio of the trench is decreased, and the cell pitch of the transistor is increased. Thus, it is difficult to miniaturize the device.
The present invention has been made in view of the above aspects with an object to provide a method for manufacturing a semiconductor device having a suppressed number of crystal defects without decreasing the aspect ratio. To accomplish the object, in the present invention, hydrogen annealing is applied to reduce the crystal defects.
In this invention, in a semiconductor device, an insulator layer is formed on a surface of a wall defining a trench in a semiconductor layer after annealing the trench in a hydrogen atmosphere. The crystal defects generated in a crystal adjacent to the trench are cured by the hydrogen annealing without enlarging the trench horizontally, so that a trench having a high aspect ratio is provided while the breakdown voltage of the insulator layer is prevented from being lowered. In addition, in the case that the trench is formed across a PN junction, leak current at the PN junction is prevented as well.